1. Field of the Invention
The present invention relates to a method for defining two self-aligned areas at the upper surface of a substrate.
The present invention more specifically applies to the manufacturing of semiconductor components, and especially of integrated circuits.
2. Discussion of the Related Art
During manufacturing of integrated circuits, it is usual to perform many photoetching steps to define successive areas and layers on a semiconductor substrate. However, it is well known that areas defined by two distinct photolithographic steps (two distinct masks) cannot be ideally aligned due to the inevitable alignment tolerance between two successive masks.
Various self-alignment methods have thus been developed to obtain areas defined on the upper surface of a substrate and separated by precise distances.
A general example of a self-alignment technique using spacers is illustrated in FIG. 1. An active area delimited by an insulating region 2 is defined on a substrate 1. In the case of semiconductor substrates, region 2 typically is a thick oxide region, for example a layer formed by the LOCOS method, or, as in the example shown, an oxide formed in a trench made in the substrate. Then, a layer 3 that is opened in a region 4 located above a portion of the active area is deposited. After this, a spacer 5 is conventionally formed at the border of the opened region. A first area A1 arranged on the front side of the spacer and a second area A2 arranged on the rear side of the spacer are thus defined. The distance between these areas does not depend on the successive positioning of two masks but only on the spacer length, that is, on the thickness of layer 3 and on the formation mode of the spacer. In the case where substrate 1 is a semiconductor, area A1 will, for example, undergo a dopant implantation and area A2 will, for example, be modified by a dopant contained under the lower portion of layer 3, which will also, or instead of this, be a contacting layer.
A known example of application of this conventional method to the forming of the base-emitter region of an NPN transistor is illustrated in FIGS. 2A and 2B.
As illustrated in FIG. 2A, an active area of a substrate 1 is delimited by a thick oxide trench 2. On this structure are successively formed a P-type doped polysilicon layer 11 and a silicon oxide layer 12. A central opening 4 is etched. A thermal oxidation step enables forming a thin oxide layer 13 on all the exposed silicon surfaces. A P-type dopant is then implanted to form intrinsic base 15 of the NPN transistor. During the anneal of this implantation, the P-type dopant contained in layer 11 starts diffusing into the substrate to form an extrinsic base region 16.
At the next steps, as illustrated in FIG. 2B, a spacer is formed, for example by successively depositing a thin silicon-nitride layer 17 and a polysilicon or silicon oxide layer 18 and by anisotropically etching layer 18, and then selectively etching layer 17 that is then masked by layer 18. Finally, an N-type doped polysilicon layer 19 is deposited, which is used as a source for the forming of a shallow N-type emitter region 20 in P-type base region 15.
Thus, the lateral distance between emitter 20 and extrinsic base 16 is defined by length d of the spacer and by the features of the manufacturing method.
The alignment method described hereabove is totally satisfactory but it should be noted that there are many circumstances under which it cannot be applied. For example, the method cannot be used if the material of layer 3 (P-type doped polysilicon 11 in the specific case of FIG. 2A) disturbs upon its deposition the substrate in area A1. A problem is also raised if, during the etching of layer 3, there is a risk of alteration of the properties of area A1. This last problem is for example raised if the upper surface of the substrate is covered with a thin active layer, for example, SiGe, and if layer 3 is polysilicon; the polysilicon etching will generate a strong risk of overetching of SiGe.
Thus, the present invention provides a novel method of formation of two self-aligned areas on a semiconductor substrate.
The present invention provides such a method that is especially applicable to the case where the localized areas are defined on an epitaxial silicon-germanium layer.
Another object of the present invention is to form an NPN transistor structure with a silicon-germanium base.
To achieve these and other objects, the present invention provides a method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of:
depositing a protective layer;
depositing a covering layer;
opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas;
forming a spacer along the edge of the opening, this spacer having a rear portion against said border and an opposite front portion;
opening the protective and covering layers behind the rear portion of the spacer; and
removing the protection layer to reach the rear portion of the spacer;
whereby two self-aligned areas are defined on either side of the spacer length.
According to an embodiment of the present invention, the method includes the step of inserting a material in the space between the substrate and the covering layer.
According to an embodiment of the present invention, said material is adapted to diffusing into the substrate under the remaining portion of the covering layer.
According to an embodiment of the present invention, the substrate is a semiconductor substrate of a first conductivity type coated with a layer of the opposite conductivity type at a low doping level, the protective layer is made of silicon oxide, and the covering layer is formed of the superposition of a doped polysilicon layer of the second conductivity type and of a silicon nitride layer.
According to an embodiment of the present invention, after the step of removing the protective layer, it is provided to uniformly deposit a conductive layer, for example a polysilicon layer, by chemical vapor deposition.
According to an embodiment of the present invention, the layer of the opposite conductivity type at a low doping level is a silicon-germanium epitaxial layer.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.